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| 0603CS-56NXJLW资料 | |
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0603CS-56NXJLW PDF Download |
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File Size : 116 KB
Manufacturer: Description:The Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter- nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：0603CS-56NXJLW 厂 家： 封 装：08＋ 批 号：28000 数 量： 说 明：原装现货 |
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运 费： 所在地： 新旧程度： |
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| 联系人：林小姐 |
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