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| 3296Y-1-202LF资料 | |
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3296Y-1-202LF PDF Download |
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File Size : 116 KB
Manufacturer:BOURNS Description:ADSC write accesses are initiated when the following condi- tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BW[A:D]) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQX is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：3296Y-1-202LF 厂 家：BOURNS 封 装：09+ 批 号：3296Y 数 量： 说 明：10000 |
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