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| ACL3225S-470K-T资料 | |
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ACL3225S-470K-T PDF Download |
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File Size : 116 KB
Manufacturer:TDK Description:With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low. When LDAC is high during serial programming, the new value is stored within the device and can be transferred to the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered most significant bit (MSB) first. Data transfers using two 8-clock cycle periods are shown in Figures 3 and 4. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：ACL3225S-470K-T 厂 家：TDK 封 装：08＋ 批 号：9,000 数 量： 说 明：原装现货 |
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