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| BLM21AJ401SN1D资料 | |
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BLM21AJ401SN1D PDF Download |
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File Size : 116 KB
Manufacturer: Description:The interface between the IOBs and core logic has been redesigned in the XC5200 family. The IOBs are completely decoupled from the core logic. The XC5200 IOBs contain dedicated boundary-scan logic for added board-level test- ability, but do not include input or output registers. This approach allows a maximum number of IOBs to be placed around the device, improving the I/O-to-gate ratio and decreasing the cost per I/O. A freeway of interconnect cells surrounding the device forms the VersaRing, which provides connections from the IOBs to the internal logic. These incremental routing resources provide abundant connections from each IOB to the nearest VersaBlock, in addition to Longline connections surrounding the device. The VersaRing eliminates the historic trade-off between high logic utilization and pin placement flexibility. These incremental edge resources give users increased flexibility in preassigning (i.e., locking) I/O pins before completing their logic designs. This ability accelerates time-to-market, since PCBs and other system components can be manu- factured concurrent with the logic design. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：BLM21AJ401SN1D 厂 家： 封 装：08＋ 批 号：4000 数 量： 说 明：原装现货 |
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运 费： 所在地： 新旧程度： |
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