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| BLM21BD601SN1D资料 | |
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BLM21BD601SN1D PDF Download |
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File Size : 116 KB
Manufacturer: Description:The clock input is differential and TTL/CMOS-compatible. The 10-bit digital outputs can be operated from 3.3 V (2.5 V to 3.6 V) supplies. Two output buses support demultiplexed data up to 105 MSPS rates, and binary or twos complement output coding format is available. A data sync function is provided for timing- dependent applications. An output clock simplifies interfacing to external logic. The output data bus timing is selectable for parallel or interleaved mode, allowing for flexibility in latching output data. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：BLM21BD601SN1D 厂 家： 封 装：08＋ 批 号：1000 数 量： 说 明：原装现货 |
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运 费： 所在地： 新旧程度： |
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