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| BLM21RK121SN1D资料 | |
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BLM21RK121SN1D PDF Download |
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File Size : 116 KB
Manufacturer: Description:In LVDS (low-voltage differential signaling), an integrated phase lock loop multiplies the incoming ADC sampling clock by a factor of 6. This high-frequency LVDS clock is used in the data serialization and transmission process and is converted to an LVDS signal for transmission in parallel with the data. Providing this additional LVDS clock allows for easy delay matching. The word output of each internal ADC is serialized and transmitted either MSB or LSB first. The bit following the rising edge of the ADC clock output is the first bit of the word. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：BLM21RK121SN1D 厂 家： 封 装：08＋ 批 号：20000 数 量： 说 明：原装现货 |
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