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DLP31SN551ML2L

DLP31SN551ML2L资料
DLP31SN551ML2L
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Description:Jitter and other spurious outputs induced by externally generated electrical noise on VCC or mechanical vibration are not included. Dedicated external voltage regulation and careful PCB layout are recommended for optimum performance. Applies to period jitter of Q and Q. Measurements are made with the Tektronix CSA803 signal analyzer with at least 1000 samples. Period jitter measured with a 200 mVP-P sine wave swept from 1 MHz to one-half of fO at the VCC power supply terminal. The outputs are enabled when Terminal 8 is at logic HIGH. Propagation delay is defined as the time from the 50% point on the rising edge of ENABLE to the 90% point on the rising edge of the output amplitude or as the fall time from the 50% point to the 10% point. (SEE: Timing Definitions.)
 
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型 号:DLP31SN551ML2L
厂 家:
封 装:SMD
批 号:09+
数 量:700
说 明:原装现货
 
 
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