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DO3316P-683资料 | |
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DO3316P-683 PDF Download |
File Size : 116 KB
Manufacturer: Description:The DO3316P-683SXL processor core is an implementation of the protected mode 486 instruction set architecture, optimized using a RISC-like design philosophy for embedded applica- tions. Using this approach, the most frequently used instruc- tions are optimized, and on an average execute in a lower number of clock cycles than a 486. The DO3316P-683SXL features a three stage pipeline, efficient in- struction prefetching mechanism, and single cycle instruc- tion decoding for most instructions. Additionally, a 1 Kbyte in- struction cache and single cycle DRAM access provide higher memory performance than a larger unified cache implementation. The DO3316P-683SXL processor provides the same programming model and register set as the standard 486 except that real mode, virtual memory, and floating point support have been eliminated. These features have little or no impact in embed- ded applications and save significant silicon real estate. At reset, unlike the standard 486, the DO3316P-683SXL starts up in protected mode instead of real mode. All 486 instructions appropriate to protected mode and our hardware configura- tion are supported, including debug instructions. The DO3316P-683SXL is initially available to run 25 MHz at 5V. The processor clock is obtained by dividing the crystal frequency by two. For example, a 25 MHz DO3316P-683SXL runs with a 50 MHz crystal oscillator as the master clock. As a result of our innovative design, the DO3316P-683SXL achieves performance equivalent to a standard 486 with less circuitry. This translates into reduced power consumption and a lower overall system cost. It also makes the DO3316P-683SXL ideal for green systems and battery operated systems. |
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1PCS | 100PCS | 1K | 10K | ||
价 格 | |||||
型 号:DO3316P-683 厂 家: 封 装:08+ 批 号:9 X 1K 数 量: 说 明:原装现货 |
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