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| EXCCL3225U1资料 | |
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EXCCL3225U1 PDF Download |
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File Size : 116 KB
Manufacturer: Description:Once the deserializer has synchronized to the serializer, the LOCK pin transitions low. The deserializer locks to the embedded clock and uses it to recover the serialized data. ROUTx data is valid when LOCK is low, otherwise ROUT0 C ROUT9 is invalid. The ROUT0CROUT9 data is strobed out by RCLK. The specific RCLK edge polarity to be used is selected by the RCLK_R/F input. The ROUT0 C ROUT9, LOCK and RCLK outputs can drive a maximum of three CMOS input gates (15-pF load, total for all three) with a 40-MHz clock. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：EXCCL3225U1 厂 家： 封 装：08＋ 批 号：198940 数 量： 说 明：原装现货 |
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