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HZ0805E601R-00资料 | |
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HZ0805E601R-00 PDF Download |
File Size : 116 KB
Manufacturer: Description:Efficient 16-bit 56800 family controller engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency Single-cycle 16 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with unique processor addressing modes Hardware DO and REP loops Three internal address buses and one external address bus Four internal data buses and one external data bus Instruction set supports both DSP and controller functions Controller style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/OnCE debug programming interface |
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1PCS | 100PCS | 1K | 10K | ||
价 格 | |||||
型 号:HZ0805E601R-00 厂 家: 封 装:08+ 批 号:778896 数 量: 说 明:原装现货 |
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