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HZ1206E601R-00资料 | |
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HZ1206E601R-00 PDF Download |
File Size : 116 KB
Manufacturer: Description:The FS612509 is a low skew, low jitter CMOS zero-delay phase-lock loop (PLL) clock buffer IC designed for high- speed motherboard applications, such as those using 133MHz SDRAM. Nine buffered clock outputs are derived from an onboard open-loop PLL. The PLL aligns the frequency and phase of all output clocks to the input clock CLK, including an FBOUT clock that feeds back to FBIN to close the loop. One group of five outputs 1Y0 to 1Y4 are enabled and disabled low by the active-high 1G signal. A second group of four outputs 2Y0 to 2Y3 are enabled and dis- abled low by the active-high 2G signal. The PLL may be bypassed by pulling AVDD to ground. |
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1PCS | 100PCS | 1K | 10K | ||
价 格 | |||||
型 号:HZ1206E601R-00 厂 家: 封 装:08+ 批 号:6000 数 量: 说 明:原装现货 |
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