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| LQH32CN100K53L资料 | |
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LQH32CN100K53L PDF Download |
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File Size : 116 KB
Manufacturer: Description:Mode Register Set options include the length of pipeline ( CAS latency of 2 / 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 2 / 4 / 8), and the burst count sequence(sequential or interleave). Because data rate is doubled through reading and writing at both rising and falling edges of the clock, 2X higher data bandwidth can be achieved than that of traditional (single data rate) Synchronous DRAM. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：LQH32CN100K53L 厂 家： 封 装：08＋ 批 号：18100 数 量： 说 明：原装现货 |
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