|
|||||||
|
|||||||
|
|
|
|||||||
|
|||||||
|
|
| LQW18AN3N9C10D资料 | |
|
LQW18AN3N9C10D PDF Download |
|
File Size : 116 KB
Manufacturer: Description:can default to one of four preselected offsets Dedicated serial clock input for serial programming of flag offsets User selectable input and output port bus sizing -x40 in to x40 out -x40 in to x20 out -x40 in to x10 out -x20 in to x40 out -x10 in to x40 out Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Empty and Full flags signal FIFO status Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Output enable puts data outputs into High-Impedance state JTAG port, provided for Boundary Scan function 208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch Easily expandable in depth and width Independent Read and Write Clocks (permit reading and writing simultaneously) High-performance submicron CMOS technology Industrial temperature range (-40C to +85C) is available |
|
| 相关型号 | |
| ◆ STM32H745ZIT6 | |
| ◆ FT838NB1-RT | |
| ◆ AO4485 | |
| ◆ RFANT5220110A0T | |
| ◆ RFANT3216120A5T | |
| ◆ P13-I39606 | |
| ◆ DF30FC-40DS-0.4V(82) | |
| ◆ JS202011SCQN | |
| ◆ 2041119-1 | |
| ◆ 541044031 | |
| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
|
型 号：LQW18AN3N9C10D 厂 家： 封 装：08＋ 批 号：20000 数 量： 说 明：原装现货 |
|||||
|
运 费： 所在地： 新旧程度： |
|||||
| 联系人：林小姐 |
| 电 话：0755-83041767,82716726 |
| 手 机：13570833454 |
| QQ：133289964,506456591,1062431938 |
| MSN：RFDZ0754@126.COM |
| 传 真：0755-82716726 |
| EMail：rxdz0754HK@126.com |
| 公司地址： 深圳市福田区华强北佳和大厦4C143 |
