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| MEM2012T35R0T0S1资料 | |
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MEM2012T35R0T0S1 PDF Download |
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File Size : 116 KB
Manufacturer: Description:S3901/S3904 series do not require any DC voltage supply for operation. However, the Vss, Vsub and all NC terminals must be grounded. A start pulse öst and 2-phase clock pulses ö1, ö2 are needed to drive the shift register. These start and clock pulses are positive going pulses and CMOS logic com- patible. The 2-phase clock pulses ö1, ö2 can be either completely separated or complementary. However, both pulses must not be High at the same time. A clock pulse space (X1 and X2 in Figure 7) of a rise time/fall time - 20 ns or more should be input if the rise and fall times of ö1, ö2 are longer than 20 ns. The ö1 and ö2 clock pulses must be held at High at least 200 ns. Since the photodiode signal is obtained at the rise of each ö2 pulse, the clock pulse frequency will equal the video data rate. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：MEM2012T35R0T0S1 厂 家： 封 装：08＋无铅 批 号：3450 数 量： 说 明：原装现货 |
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