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| MM3Z5V1T1G资料 | |
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MM3Z5V1T1G PDF Download |
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File Size : 116 KB
Manufacturer:ON Description:The MM3Z5V1T1G and MM3Z5V1T1G are synchronous SRAM designed to support the burst address accessing sequence of the P6 and Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV. When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：MM3Z5V1T1G 厂 家：ON 封 装：2009 批 号：65000 数 量：SOD-323 说 明： |
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