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| MMSZ12T1资料 | |
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MMSZ12T1 PDF Download |
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File Size : 116 KB
Manufacturer:ON Description:When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condi- tion. In this way, up to 8 ST24/25E64 may be connected to the same I2C bus and selected indi- vidually, allowing a total addressing field of 512 Kbit. Power On Reset: VCC lock out write protect. In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Untill the VCC voltage has reached the POR threshold value, the internal reset is active: all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：MMSZ12T1 厂 家：ON 封 装：2009 批 号：65000 数 量：SOD-123 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：林小姐 |
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