|
|||||||
|
|||||||
|
|
|
|||||||
|
|||||||
|
|
| MMZ2012S102AT000资料 | |
|
MMZ2012S102AT000 PDF Download |
|
File Size : 116 KB
Manufacturer: Description:HighCperformance, lowCcost CMOS EEPROMCbased programmable logic devices (PLDs) built on a MAX® architecture (see Table 1) 3.3-V in-system programmability (ISP) through the builtCin IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability CISP circuitry compliant with IEEE Std. 1532 BuiltCin boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 Enhanced ISP features: CEnhanced ISP algorithm for faster programming CISP_Done bit to ensure complete programming CPull-up resistor on I/O pins during inCsystem programming HighCdensity PLDs ranging from 600 to 10,000 usable gates 4.5Cns pinCtoCpin logic delays with counter frequencies of up to 227.3 MHz MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0CV, 3.3CV, and 2.5CV logic levels Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic JClead chip carrier (PLCC), and FineLine BGATM packages HotCsocketing support Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance |
|
| 相关型号 | |
| ◆ STM32H745ZIT6 | |
| ◆ FT838NB1-RT | |
| ◆ AO4485 | |
| ◆ RFANT5220110A0T | |
| ◆ RFANT3216120A5T | |
| ◆ P13-I39606 | |
| ◆ DF30FC-40DS-0.4V(82) | |
| ◆ JS202011SCQN | |
| ◆ 2041119-1 | |
| ◆ 541044031 | |
| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
|
型 号：MMZ2012S102AT000 厂 家： 封 装：08＋ 批 号：12000 数 量： 说 明：原装现货 |
|||||
|
运 费： 所在地： 新旧程度： |
|||||
| 联系人：林小姐 |
| 电 话：0755-83041767,82716726 |
| 手 机：13570833454 |
| QQ：133289964,506456591,1062431938 |
| MSN：RFDZ0754@126.COM |
| 传 真：0755-82716726 |
| EMail：rxdz0754HK@126.com |
| 公司地址： 深圳市福田区华强北佳和大厦4C143 |
