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| MMZ2012S601A资料 | |
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MMZ2012S601A PDF Download |
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File Size : 116 KB
Manufacturer:TDK Description:Aside from jitter effects, noise and pulse distortion both reduce the phase margin in which received bits can be clocked for the purpose of sensing their logic level. The use of a phase- locked loop (PLL) is essential in synchronizing the clock with the data stream, to ensure alignment of the clock with the middle of a data word. To further optimize the bit error rate (BER) in the presence of asymmetrical rise and fall transitions of the received data signal, the system should include an option to adjust the phase relation between clock and data. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：MMZ2012S601A 厂 家：TDK 封 装：08＋ 批 号：4K 数 量： 说 明：原装现货 |
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