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| NLFC322522T-150K-PF资料 | |
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NLFC322522T-150K-PF PDF Download |
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File Size : 116 KB
Manufacturer: Description:The clock source jitter and the aperture jitter combine in an rms manner to yield the total sampling jitter. See Definition of Terms. Device aperture jitter increases as the V(CLK1) C V(CLK1B) slew rate at the zero crossing decreases. See Theory of Operation. The differential pedestal error is proportional to the input signal. For TH1 it corresponds to a track-to-hold gain ~ -0.17 dB. This gain loss may be observed at the DTH output if TH2 is in track mode during the TH1 track-to-hold transition. The variance of the hold noise is proportional to the hold time, thold. For example, for TH1, a 4-ns hold time, thold1, gives about 100 µV accumulated hold noise. TH1 and TH2 hold noise, up to the output sampling instant, should be rms added to the hold mode integrated noise of the DTH. Maximum hold time is determined by droop of single-ended hold capacitor voltages. The resulting shift of internal operating voltages is not directly observable at the DTH outputs but eventually causes device performance degradation. TH1 tacq, dvdt,max, and tr also apply to the reconstructed DTH output if sub-sampling a fast-edge repetitive wave form. Output is settled ta2 + ts2 after CLK2(B) downward transition. The differential pedestal error is proportional to the input signal. For TH2 it corresponds to a track-to-hold gain ~ 0.02 dB. ttrack2,min > ts, since the buffered TH1 output onto the TH2 hold capacitors lags behind the TH1 hold capacitor signal. The part functions immediately and reaches specification after warm-up time. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：NLFC322522T-150K-PF 厂 家： 封 装：08＋ 批 号：18700 数 量： 说 明：原装现货 |
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