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| PCA9515ADR资料 | |
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PCA9515ADR PDF Download |
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File Size : 116 KB
Manufacturer: Description: The integration time is pre-programmed via the two-wire serial interface and indicated by the EXPOSE signal going HIGH. When the sensor commences, the readout process the FRAME_VALID, ROW_VALID, and DATA signals are output, as shown in Figure 5 on page 5. The master mode row synchronization waveform relationships are as shown in Figure 5 on page 5. The FRAME_VALID signal goes HIGH, indicating the start of frame, and 2.5 clock cycles later the ROW_VALID signal goes HIGH, indicating the start of the first row. The first data bit is valid on the first falling edge of SYSCLK after ROW_VALID goes HIGH. The remaining 665 pixels for the row are valid on the subsequent fall- ing edges of SYSCLK, after which ROW_VALID returns to the LOW state. (Please note that in master mode 648 pixels are readout for each row.) The ROW_VALID will then be an active HIGH envelope for subsequent rows and the FRAME_VALID signal will be an active HIGH envelope for subsequent frames. The time required for one complete row operation is 671 clock cycles: 1 clock cycle delay + 666 columns + 4 clock cycles when ROW_VALID is LOW. With a SYSCLK of 66 MHz, this translates into a row time of 10.2µs and a frame time of 5.1ms for full resolution (502 rows). This assumes there is no vertical blanking or horizontal blanking and that the exposure time is less than 5.1ms. If exposure time becomes greater than 5.1ms, the frame time then becomes the inverse of the exposure time (1/[exposure time]). |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：PCA9515ADR 厂 家： 封 装： 批 号： 数 量： 说 明： PCA9515ADR SOP-8 全新原装正品 |
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