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PRTR5V0U2X

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PRTR5V0U2X
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Description:The KBE00S009M is a Multi Chip Package Memory which combines 2Gbit Nand Flash Memory(organized with two pieces of 1G bit Nand Flash Memory) and 512Mbit synchronous high data rate Dynamic RAM.(organized with two pieces of 256Mbit Mobile SDRAM) 2Gbit NAND Flash memory is organized as 256M x8 bits and 512Mbit SDRAM is organized as 4M x32 bits x4 banks. In 2Gbit NAND Flash, its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200µs on the 528-bytes and an erase operation can be performed in typical 2ms on a 16K- bytes block. Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/ output as well as command input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable appli- cations requiring non-volatility. In 512Mbit SDRAM, Synchronous design make a device controlled precisely with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
 
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PRTR5V0U2X

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