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SC100FT

SC100FT资料
SC100FT
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Description:Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs) The core performs branch prediction with conditional prefetch, without conditional execution 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).   C 16-Kbyte instruction cache (MPC862P) is four-way, set-associative with 256 sets; 4-Kbyte   instruction cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative   with 128 sets.   C 8-Kbyte data cache (MPC862P) is two-way, set-associative with 256 sets; 4-Kbyte data   cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative with 128 sets.   C Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)   cache blocks.   C Caches are physically addressed, implement a least recently used (LRU) replacement    algorithm, and are lockable on a cache block basis. MMUs with 32-entry TLB, fully associative instruction and data TLBs MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address   spaces and 16 protection groups Advanced on-chip-emulation debug mode The MPC862/857T/857DSL provides enhanced ATM functionality over that of the MPC860SAR. The MPC862/857T/857DSL adds major new features available in enhanced SAR (ESAR) mode, including the following: Improved operation, administration and maintenance (OAM) support OAM performance monitoring (PM) support Multiple APC priority levels available to support a range of traffic pace requirements ATM port-to-port switching capability without the need for RAM-based microcode Simultaneous MII (10/100Base-T) and UTOPIA (half-duplex) capability
 
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型 号：SC100FT
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封 装：08＋无铅
批 号：8000
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说 明：原装现货
 
 
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